CoWoS advanced packaging, TSMC Tainan

The link where already-expensive dies are assembled

Advanced packaging comes at the very end of the chain, and that is what makes it formidable. On a single silicon interposer it marries an already-etched and tested GPU (a "known good die") to several stacks of HBM memory that are themselves already stacked and costly. An assembly defect, misaligned microbumps, warpage of a giant package, delamination, does not ruin a bare silicon wafer but an assembly worth tens of thousands of dollars in finished components. Back-end yield, long negligible, becomes the dominant economic factor.

This is why capacity cannot be "caught up" by buying machines. Lining up equipment is not enough: what is needed is the process maturity that guarantees yield on ever-larger packages, at each new generation. That yield know-how, invisible in the brochures, is precisely what TSMC holds and what neither Amkor nor the Taiwanese OSATs yet match at scale.

Bigger than the reticle

The Blackwell GPUs, then Rubin, exceed the reticle limit, the maximum area (≈858 mm²) a lithography scanner can print in a single pass. TSMC works around the obstacle with CoWoS-L, which "stitches" several chiplets together using local silicon interconnect bridges (LSI), allowing packages approaching six times the area of a reticle. The interposer itself becomes an object larger than a chip, consuming silicon by whole wafers only to serve as wiring: a compute chip is now also paid for in purely passive silicon area.

Capacity nearly doubles every year, from about 35,000 wafers/month at end-2024 to ≈65,000 at end-2025, then a target of 130,000 to 150,000 at end-2026, and stays below demand. Nvidia locks up more than 60 % of the slots and prepays. Investment is not the constraint: qualifying a novel assembly chemistry at each generation takes incompressible months, on packages whose very size pushes the physical limits of the process.

Dossier sources