SK Hynix, Icheon
Near-exclusive supplier of high-bandwidth memory for high-end GPUs. A double dependency: Korea for the memory, Taiwan for its integration into the package.
HBM's silicon tax
An HBM chip is a vertical stack of DRAM dies drilled with through-silicon vias (TSV). This process, smaller dies, the surcharge of the TSVs, complex assembly, means that a gigabyte of HBM swallows roughly three to four times the wafer area of a gigabyte of standard DRAM. In other words, HBM drains a share of fab output far greater than the volume of bits it represents. TrendForce estimates that AI could absorb nearly 20 % of global DRAM wafer capacity in 2026, while that capacity grows only 10 to 15 % a year.
By capturing this capacity, HBM starves the rest of the market. The shortage and price surge of commodity DRAM (PC, smartphone, DDR5 server) in 2025-2026 follow directly from this diversion of capacity. And the shock has overturned a thirty-year hierarchy: SK Hynix, long the number two, overtook Samsung in DRAM revenue as early as the first quarter of 2025, carried by its lead in HBM. The risk no longer lies with the sole HBM maker: HBM makes all memory scarce.
Now even the memory goes through Taiwan
HBM was the last critical layer of the accelerator not to transit through Taiwan: it was Korean, end to end. That changes with HBM4. The new generation adds a logic "base die" at the bottom of the stack, and SK Hynix entrusts its fabrication to TSMC. The most recent memory thus now couples Korea (DRAM stacking) with Taiwan (base die), then Taiwan again (CoWoS integration): the same island appears three times in a single GPU.
Meanwhile, the whole of SK Hynix's 2026 output, HBM, and increasingly DRAM and NAND, is already pre-sold, largely to Nvidia. The buffer stock is zero. An incident at a single site, Icheon or Cheongju, does not dilute into an order book: it propagates instantly across the entire global AI build-out, which has no spare memory capacity to call on.